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71M6543F/71M6543G Data Sheet
The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field ( I/O RAM 0x240D[4:0 ]).
The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN
and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered
down. This setting can be used to reduce current in LCD mode.
STATIC (LCD_MODE=100)
COM0
1/2 BIAS, 2 STATES (LCD_MODE = 010 )
0 1
COM0
1/2 BIAS, 3 STATES (LCD_MODE = 011 )
0 1 2
COM0
COM1
(1/2)
COM1
COM1
COM2
(1/2)
COM2
(1/2)
COM2
COM3
COM4
COM5
(1/2)
(1/2)
(1/2)
COM3
COM4
COM5
(1/2)
(1/2)
(1/2)
COM3
COM4
COM5
(1/2)
(1/2)
(1/2)
SEG_ON
SEG_OFF
SEG_ON
SEG_OFF
T
SEG_ON
SEG_OFF
1/3 BIAS, 3 STATES (LCD_MODE = 011 )
1/3 BIAS, 4 STATES (LCD_MODE = 000 )
1/3 BIAS, 6 STATES (LCD_MODE = 110 )
0 1 2
0 1 2
3
0 1 2
3
4 5
COM0
COM1
COM2
COM0
COM1
COM2
COM0
COM1
COM2
COM3
COM4
COM5
SEG_ON
SEG_OFF
(2/3)
(1/3)
COM3
COM4
COM5
SEG_ON
SEG_OFF
COM3
COM4
COM5
SEG_ON
SEG_OFF
Figure 17: LCD Waveforms
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM registers LCD_SEG46[5:0] through LCD_SEG50[5:0] (see Table 53) .
Table 53: LCD Data Registers for SEGDIO46 to SEGDIO55
SEGDIO
Pin #
46
93
47
92
48
58
49
57
50
56
51
53
52
52
53
51
54
47
55
46
Configuration:
Always LCD pins
See 2.5.10.2
SEG Data
Register
The LCD_MAP[47:46] ( I/O RAM 0x2406[7:6] ) bits are used to determine whether SEG46 and SEG47 are
SEG pins or their alternate function (see pins 93 and 92 in Figure 42 ). If the LCD_MAP[47:46] bits are 1,
then the pins are configured as SEG pins. If the LCD_MAP[47:46] bits are 0, then the pins are configured
as their alternate functions (TMUX2OUT and TMUXOUT, respectively).
64
v2
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